In a research paper named "XEEMU: An Improved XScale Power Simulator" we describe the creation of XEEMU in more detail. This paper was presented at the PATMOS conference held in Gothenburg, Sweden, in September 2007. If you are interested in this paper, please have a look at the abstract or you can also download the PDF slides of the presentation.
XEEMU was developed to simulate the runtime and power consumption of the Intel(c) XScale(c) core as closely as possible. Therefore, the powermodel was modeled to match measurements on the ADI 80200 EVB evaluation board. Hardware measurements were done using a Tektronix TPS 2014 digital storage oscilloscope.
Below you can see results for simulation and measurement of our benchmark set, as well as a chart comparing the simulated and measured instantaneous power consumption of the XScale core for two benchmark programs. It can clearly be seen that the simulator accurately simulates the instantaneous power consumption in different regions of a program. Be aware, that measurements on hardware are always prone to noise.

We also compared our simulator to XTREM, another open-source XScale simulator which we found to be much less accurate.

XEEMU is also capable of simulating the power consumption of the SDRAM subsystem, making it a really unique tool for system power optimization. Earlier versions incorporated a power model provided by the SDRAM manufacturer Micron. While this power model is still present, XEEMU now also features a new power model, which is based on measurements on the evaluation board and proved to be much more accurate in the average case, oposed to Micron's worst case model. This new SDRAM power model has been published at the SBCCI conference in 2009.